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73M2901/3.3V
Advanced Single Chip Modem
December 2000
DESCRIPTION
The 73M2901/3.3V is a single-chip modem that combines all the controller (DTE) and data pump functions necessary to implement an intelligent V.22bis data modem. This device is based on TDK Semiconductor's implementation of the industry standard 8032 microcontroller core with a proprietary multiply and accumulate (MAC) coprocessor; SigmaDelta A/D and D/A converters; and an analog front end. The ROM and RAM necessary to operate the modem are contained on the device. Additionally, the 73M2901/3.3V provides an on-chip oscillator and Hybrid driver. The 73M2901/3.3V is a high performance, low voltage, low power, single chip modem capable of data transmission and reception through 2400bps. The 73M2901/3.3V is intended for embedded applications and battery operation. This device offers low power 3.3 volt design with optional internal hybrid and country specific call progress support.
FEATURES
* * * * * * Low overall system chip count. True one chip solution for embedded systems Low operating power (~120mW @ 3.3V, automatic low power standby and power down options available) Internal ROM and RAM for normal operation On chip optional hybrid driver Designed for +3.15 through +3.6 volts Data speeds: V.22bis - 2400bps V.22, Bell 212 - 1200bps V.21, Bell 103 - 300bps V.23 - 1200/75bps (w/ turnaround (PAVI)) Bell 202 - 1200bps Bell 202 and V23 4-wire operations Dynamic Range: -9dBm to -43 dBm "AT" command set Host access to modem port pins via AT commands for custom I/O expansion DTMF tone generation and detection Call progress support with multinational options (FCC68, CTR21, JATE...) Caller ID capability Blacklisting capability Packaging: 32 pin PLCC or 44 pin TQFP
* * * * * * * *
BLOCK DIAGRAM
RAM
ASRCH RING DTR TxCLK TxD RxD RxCLK
ROM
CPU AFE
MAC
Hybrid
RxA TxAP TxAP
RI CTS DCD DSR RTS
USR10 USR11 RELAY
HBDEN
73M2901/3.3V Advanced Single Chip Modem
HARDWARE DESCRIPTION
The 73M2901/3.3V is designed for a single +3.3 volt supply with low power consumption (~120mW @ 3.3 volts). The modem supports automatic standby idle mode. The modem will also accept a request to power down from the DTE via hardware control. No additional major components are required to complete the modem core logic. The modem provides direct firmware LED support via port pins. HARDWARE FEATURES * * * * * * Fully self-contained. "AT" Command interpreter and data pump User pin available Synchronous serial data I/O available Asynchronous serial port On-chip hybrid driver. Autobaud capability from 300bps to 9600bps The hybrid configuration is controlled by the state of the HBDEN pin. For driving a line-coupling transformer, HBDEN should be pulled high. For driving an external hybrid (load on TXAP and TXAN is 50k or larger), HBDEN should be pulled low. The 73M2901/3.3V provides firmware control for a hook relay driver (RELAY) as well as interrupt support for a ring detect opto-coupler (RING). INTERRUPT PINS The external interrupt sources, DTR, ASRCH and RING, come from dedicated input pins of the same name.
DTR informs the 73M2901/3.3V that the host has requested the 73M2901/3.3V perform a specific function. The actual particulars of that function can be changed by "AT" commands (described in full in the TDK 73M2901 User's Guide). ASRCH informs the 73M2901/3.3V that the host is passing data to the 73M2901/3.3V over the DTE interface. This instructs the 73M2901/3.3V to begin looking for valid "AT" commands. This pin needs to be connected to the TXD pin. RING informs the 73M2901/3.3V that the external DAA circuitry has detected a ring signal.
POWER SUPPLY Power is supplied to the 73M2901/3.3V via the VPD and VPA pins. The 73M2901/3.3V is designed for a single +3.15 through +3.6 volt supply and for low power consumption (~120mW @ 3.3 volts). Ground Reference is provided at the VND and VNA pins. LOW POWER MODE The TDK 73M2901/3.3V supports a low power mode. If the low power standby option is enabled the 73M2901/3.3V will go into a power saving mode when idle. The oscillator will be running, clocks will be supplied to the UART, timers and interrupt blocks; but no clocks will be supplied to the CPU. Instruction processing and activity on the internal busses is halted. Normal operation is resumed when an interruption such as DTR, RING or ASRCH (any character send to the 73M2901/3.3V) is requested or when a reset occurs. ANALOG LINE / HYBRID INTERFACE The 73M2901/3.3V provides a differential analog output (TXAP and TXAN) and a single-ended analog input (RXA) with internal A/D and D/A converters. A driver is provided for an internal hybrid function. The internal hybrid driver is capable of driving an external load matching impedance and a linecoupling transformer. If an external hybrid is to be used, the on-chip hybrid drivers can be reconfigured to drive a minimum load of 50k and thus reduce the driver's power consumption. 2
CRYSTAL OSCILATOR The TDK 73M2901/3.3V single chip modem can use an external 11.0592 MHz reference clock or can generate such a clock using only a crystal and two capacitors. If an external clock is used, it should be applied to OSCIN. SPECIFYING A CRYSTAL The manufacturer of a crystal resonator verifies its frequency of oscillation in a test set-up, but to ensure that the same frequency is obtained in the application, the circuit conditions must be the same. The TDK 73M2901/3.3V modem requires a parallel mode (antiresonant) crystal, the important specifications of which are as follows: Mode: Frequency: Frequency tolerance: Temperature drift: Load capacitance: ESR: Drive level: Parallel (antiresonant) 11.0592 MHz 50 ppm at initial temperature. 50 ppm additional over full Range. 18pF or 20pF 75 max. Less than 1mW.
73M2901/3.3V Advanced Single Chip Modem
RESET A reset is accomplished by holding the RESET pin high. To ensure a proper power-on reset, the reset pin must be held high for a minimum of 3s. At power on, the voltage at VPD, VPA, and RESET must come up at the same time for a proper reset. ASYNCHRONOUS AND SYNCHRONOUS SERIAL DATA INTERFACE The serial data interface consists of the TXD and RXD data paths (LSBit shifted in and out first, respectively); and the TXCLK and RXCLK serial clock outputs associated with the data pins; CTS/RTS flow control; DCR, DSR and DTR. In synchronous mode, the data is passed at the bit rate (tolerance is +1%, -2.5%).
PIN DESCRIPTIONS
POWER PIN DESCRIPTION PIN NAME VPA VNA VPD VND 32-PIN 44-PIN 15 21 6, 25, 29 5, 22, 26 16 22 2,12, 27, 33 11, 24, 44, 28 TYPE I I I I DESCRIPTION Positive analog voltage (+ Analog Supply) Negative analog voltage. (Analog Ground) Positive digital voltage (+ Digital Supply) Negative digital voltage. (Digital Ground)
ANALOG INTERFACE PIN DESCRIPTION PIN NAME RXA TXAN TXAP HBDEN 32-PIN 44-PIN 20 16 17 14 21 17 18 15 TYPE I O O I DESCRIPTION Receive analog data Transmit Analog Transmit Analog + 2w/4w hybrid driver enable pin 0 = Driver configured for 50k or greater load (Tie to VND) 1 = Driver configured for driving line-coupling transformer (Tie to VPD) VBG VREF 19 18 20 19 O O Analog Band Gap voltage reference pin (0.1F to VNA) Analog reference voltage pin (0.1F to VNA)
EXTERNAL INTERRUPTS PIN DESCRIPTIONS PIN NAME
RING ASRCH DTR
32-PIN 44-PIN 2 1 32 39 38 37
TYPE I I I
DESCRIPTION External interrupt - Line interface ring detection circuitry input External interrupt - Autobaud detection, connected to TXD External interrupt - DTE DTR signal input
3
73M2901/3.3V Advanced Single Chip Modem
PIN DESCRIPTIONS (continued)
OSCILLATOR PIN DESCRIPTION PIN NAME OSCIN OSCOUT 32-PIN 44-PIN 24 23 26 25 TYPE I O DESCRIPTION Crystal input for internal oscillator, also input for external source. Crystal oscillator output.
DIGITAL INTERFACE PIN DESCRIPTION PIN NAME RESET RXCLK RXD TXCLK TXD USR10 32-PIN 44-PIN 13 31 30 28 27 12 9 36 35 31 30 8 TYPE I O O O I I/O DESCRIPTION Resets 73M2901/3.3V Receive Data Synchronous Clock Serial output to DTE. Transmit Data Synchronous Clock Serial data input from DTE. This pin can optionally be configured as an active low detect pin. This can be used to implement such functions as "parallelpick-up", "line-in-use", or "seize" detect. Programmable I/O port. This pin can ooptionnaly be used to control an external switch for Caller ID decoding operations. Request to Send Clear to Send Data Set Ready Data Carrier Detect Ring Indicator Relay driver output
USR11
RTS (USR12) CTS (USR13) DSR (USR14) DCD (USR15) RI (USR16) RELAY (USR17)
11 10 9 8 7 4 3
7 6 5 4 3 43 40
I/O I O O O O O
4
73M2901/3.3V Advanced Single Chip Modem
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS Operation above maximum rating may permanently damage the device. PARAMETER Supply Voltage Pin Input Voltage Storage Temperature RECOMMENDED OPERATING CONDITIONS PARAMETER Supply Voltage Oscillator Frequency Operating Temperature TRANSMITTER PARAMETER ITU Guard Tone Power Calling Tone Answer Tone Power DTMF Transmit Power CONDITIONS 550Hz (relative to carrier) 1800Hz (relative to carrier) 1300Hz 2225/2100Hz High band tones Low band tones MIN -5 -8 -11 -11 -8.0 -10 NOM -3.5 -6.5 MAX -2 -5 -9.0 -9.0 -6.0 -8.0 UNIT dB dB dBm0 dBm0 dBm0
1 1 1
RATING -0.5V to +7.0V -0.5V to VPD + 0.5V -55C to 150C
RATING 3.15V - 3.6V 11.0592MHz +/- 50ppm -40C to +85C
MAXIMUM TRANSMIT LEVELS Vref =1.25V; VPA = 3.3V QAM DPSK FSK DTMF (high tone) DTMF (low tone) DTMF (total) -9.6 -7.4 -5.3 -7.9 -9.8 -5.7
Note: The recommended DAA (see the TDK 73M2901 Reference Manual) will result in approximately 8dB loss from the transmit pins to the phone line. This includes the loss through the line matching impedance (475 resistor), transformer, and solid state off-hook relay. dBm0 refers to the TDK recommended DAA ( 8dB loss from Transmit pins to the line and 5dB loss from the line to the Receive pin). Results may vary depending on selected DAA. 0dBm = 0.775Vrms. dBm = 10log {Vrms2/[(1mW)(600)]}
1
5
73M2901/3.3V Advanced Single Chip Modem
ELECTRICAL SPECIFICATIONS (continued)
TRANSMITTER PARAMETER Gain Adjust Tolerance Total Harmonic Distortion (THD) CONDITIONS By step 1Khz sine wave at output (TXAP-TXAN) 1.5Vpk(2.7dBm) for Vref=1.25V THD = 2 and 3 harmonic. Intermod Distortion At output (TXAP-TXAN) 1.0kHz, 1.2 kHz sine waves summed 2.0Vpk for Vref=1.25V Refer to CTR21 specification for complete description of requirements each unwanted frequency component sum of unwanted frequency components in pass band -33 dB
nd rd
MIN -0.3
NOM 0
MAX 0.3
UNIT dB
-50
dB
-20
dB below low tone dB
Power Supply Rejection Ratio
-30 dBm signal at VPA 300Hz - 30kHz. Measured TXAP to TXAN.
30.0
RECEIVER PARAMETER Carrier Detect On Carrier Detect Off Carrier Detect Hysteresis Receive Level Idle Channel Noise CONDITIONS Tip and Ring Tip and Ring Tip and Ring Tip and Ring 0.2kHz - 4.0kHz -43.0 -70 MIN -43.0 -48.0 2.0 -9.0 -65 NOM MAX UNIT dBm0 dBm0 dB dBm0 dB
1 1 1
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73M2901/3.3V Advanced Single Chip Modem
ELECTRICAL SPECIFICATIONS (continued)
RECEIVER (continued) PARAMETER Input Impedance Receive Gain Boost Maximum Input Level at RXA Total Harmonic Distortion (THD) TEST CONDITION RXA SFR 96h bit 2 (Rxgain) = 1 VREF=1.25V 1kHz 450mV-pk on RXA THD = 2 and 3 harmonic.
nd rd
MIN 150 2.7
NOM --3.0
MAX --3.3 0.587
UNITS k dB Vpk dB
-70
-50
DC CHARACTERISTICS PARAMETER Input Low Voltage (Except OSCIN,RESET) Input Low Voltage OSCIN,RESET Input High Voltage (Except OSCIN,RESET) Input High Voltage OSCIN,RESET Output Low Voltage (Except OSCOUT) Output Low Voltage OSCOUT Output High Voltage (Except OSCOUT) Output High Voltage OSCOUT Input Leakage Current (Except OSCIN) Input Leakage Current OSCIN SYMBOL VIL VIL VIH VIH VOL VOLOSC VOH VOHOSC IIH IIH IOL = 4mA IOL = 3.0mA IOH = -4mA IOH =-3.0mA Vss < Vin < Vcc Vss < Vin < Vcc 1 Vcc - 0.45 Vcc - 0.9 1 30 CONDITION MIN -0.5 -0.5 0.5 Vcc 0.7 Vcc NOM MAX 0.2Vcc 0.2 Vcc Vcc + 0.5 Vcc + 0.5 0.45 0.7 UNIT V V V V V V V V A A
7
73M2901/3.3V Advanced Single Chip Modem
ELECTRICAL SPECIFICATIONS (continued)
DC CHARACTERISTICS PARAMETER 3.3V Operations Maximum Power Supply Normal Operation @ 3.3V HBDEN pulled high Maximum Power Supply Normal Operation @ 3.3V HBDEN pulled low Maximum Digital Power Supply @ 3.3V Maximum Analog Power Supply @ 3.3V HBDEN pulled high Maximum Analog Power Supply @ 3.3V HBDEN pulled low Maximum Power Supply Idle Mode @ 3.3V Maximum Power Supply Power Down Mode @ 3.3V PARAMETER Vbg Vref IDD1 30pF/pin 37 46 mA SYMBOL CONDITION MIN NOM MAX UNIT
IDD1
30pF/pin
22
28
mA
IDDd IDDah1
30pF/pin 30pF/pin
19 18
23 23
mA mA
IDDah0
30pF/pin
3
5
mA
IDD2 IDD3
30pF/pin 30pF/pin
7 3
9 5
mA A
CONDITION Vcc=3.3V Vcc=3.3V
MIN 1.19 1.19
NOM 1.25 1.25
MAX 1.31 1.31
UNIT V V
NOTE : The TDK 73M2901/3.3V is also tested and suitable for operations at 5 volt supply. Please refer to the 73M2901/5V Data Sheet for details.
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73M2901/3.3V Advanced Single Chip Modem
FIRMWARE DESCRIPTION2
An "AT" command interpreter provides command and configuration of the 73M2901/3.3V. This provides the user a uniform interface to control the modem in embedded applications. The signal processing is performed by obtaining data from and providing data to the integrated A/D converter. A MAC hardware processor is provided for computation. To provide maximum flexibility, the system host processor can access the internal RAM and Control Register space in the modem. This will allow the OEM user to modify parameters such as filter response, transmit levels through the AT command set using proprietary commands. The host processor can also access the modem I/O port pins, providing extended I/O capability. FIRMWARE REQUIREMENTS The modem always powers up in the idle (on hook) mode. "AT" commands are issued via the serial interface from the host. All modem configuration commands are received in this manner. The data modem firmware is contained in an internal ROM. The firmware will automatically enter a power saving idle mode if the modem is on hook and there are no incoming host commands. The modem automatically powers up upon receiving the next command. This power up sequence occurs without delay to the host. This function, while saving power, is transparent to the host processor and can be disabled by the host via an "AT" command. The host can also program the modem to power down via external pin (DTR) or via a firmware command. FIRMWARE FEATURES * * * * * "AT" command set Supports data standards through V.22bis Provides DAA control firmware (e.g. ring detect, hook control, line in use detection support) Multinational Call progress support (FCC68, CTR21, JATE...) Caller ID capability FSK demodulation (V23 or Bell202) st nd Intra 1 /2 ring CID data operations Post Line reversal CID data operations Interfaces with standard V.24/EIA-232 (3-5 volt inverted level) serial interface using the built in serial port and firmware control of port pins Provides tone generation and detection, four imprecise and four precise call progress detect filters Host access to program RAM provided User access to modem functions
* * * *
For a detailed description of the firmware consult the TDK 73M2901 User's Manual.
2
9
73M2901/3.3V Advanced Single Chip Modem
DESIGN CONSIDERATIONS
TDK Semiconductor's single chip modem solutions include all the basic modem functions. This makes these devices adaptable to a variety of applications. Unlike digital logic circuitry, modem designs must contend with precise frequency tolerances and verify low level analog signals, to ensure acceptable performance. Using good analog circuit design practices will generally result in a sound design. The crystal oscillator should be held to a 50ppm tolerance. Following are additional recommendations that should be taken into consideration when starting new designs. LAYOUT CONSIDERATIONS Good analog/digital design rules must be used to control system noise in order to obtain high performance in modem designs. The more digital circuitry present in the application, the more attention to noise control is needed. High speed, digital devices should be locally bypassed, and the telephone line interface and the modem should be located next to each other near where the telephone line connection is accessed. It is recommended that power supplies and ground traces should be routed separately to the analog and digital portions on the board. Digital signals should not be routed near low level analog or high impedance analog traces. The 73M2901/3.3V should be considered a high performance analog device. A 10F electrolytic capacitor in parallel with a 0.1F Ceramic capacitor should be placed between VPD and VND as well as between VPA and VNA. A 0.1F ceramic capacitor should be placed between VREF and VNA as well as VBG and VNA. Use of ground planes and large traces on power is recommended. The 73M2901/3.3V is the first of a series of parts with different and/or additional features. In order to insure full lay out compatibility for all the series, it is recommended to implement three additional resistors in the schematics as shown in the recommended schematics arrangement (R11, R12 and R13). TELEPHONE LINE INTERFACE Transmit levels at the line are dependent on the interface used between the pins and the line. In order to save having to provide external op-amps to drive the line coupling transformer, the analog outputs (TXAP and TXAN) have the capability to be used as the hybrid drivers for connecting to the 10 transformer directly (with the required impedance matching series resistor). Used in this configuration, there is loss associated in both the receive path and transmit path. The line interface circuit shown on the following 3 page represents the basic components and values for interfacing the TDK 73M2901/3.3V analog pins to the telephone line.
MODEM PERFORMANCE CHARACTERISTICS
The curves presented in this data sheet define modem IC performance under a variety of line conditions typical of those encountered over public service telephone lines. BER VS. SNR This test represents the ability of the modem to operate over noisy lines with a minimum amount of data transfer errors. Since some noise is generated in the best dial up lines, the modem must operate with the lowest signal to noise ratio (SNR) possible. Better modem performance is indicated by test curves that are closest to the BER axis. A narrow spread between curves representing the four line parameters indicates minimal variation in performance while operating over a range of aberrant operating conditions. Typically a DPSK modem will exhibit better BER performance test curves receiving in the low band (answer mode) than in the high band (originate mode). BER VS. RECEIVE LEVEL This test measures the dynamic range of the modem. Because signal levels vary widely over dial up lines, the widest possible dynamic range is desirable. The SNR is held constant at the indicated values as the Receive level is lowered from very a very high to a very low signal level. The width of the bowl of these curves, taken at the BER point is the measure of the dynamic range.
3
TDK73M2901 Demo boards use the line interface shown on the following page. Other designs may have different requirements and thus will require different component values or a different configuration. With the shown configuration, there is approximately an 8dB loss in the transmit path, and approximately a 5dB loss in the receive path.
73M2901/3.3V Advanced Single Chip Modem
RXA R3 21K R1 TXAP 475 C1 0.033m TXAN Midcom 671-8005 R4 5.1K T1 Telephone Line
Recommended Line Interface
VCC 1 C1 C2 10uF 2 Y1 11.0592 MHZ 27PF C3 GND R1 10K VCC 33PF GND
+
JP1 10 9 8 7 6 5 4 3 2 1 HEADER 10
13 24 23 6 25 29 26 5 22
VCC
TTL V24 signals interface
GND GND U1 2901_P32
To --> RS232 level shifter --> Host microprocessor
USR11 USR10/LIU
GND
R11
0R
RING RELAY
7 8 9 4 10 32 31 30 27 1 28
DCD DSR CTS RI RTS DTR RXC RXD TXD ASRCH TXC
RST OSCIN OSCOUT VPD VPD VPD VND VND VND
VPA VNA VREF VBG HBDEN RXA TXAP TXAN
15 21 18 19 14 20 17 16
VPA VNA C4 100nF C5 100nF VCC R2 21K
R3
5.1K 3 T1 2
PRI
11 12
2 3
R4
470 C7 .033UF
SEC
4 R12 0R R13 nc 671-8005
1
Recommended Schematics Arrangement
11
VCC
1
C1 C2 10uF Y1 11.0592 MHZ GND R1 10K VCC GND 33PF 27PF C3 GND
+
2
73M2901/3.3V Advanced Single Chip Modem
JP1 2901_P32
13 24 23 6 25 29 26 5 22
VCC
TTL V24 signals interface
GND U1
RST OSCIN OSCOUT VPD VPD VPD VND VND VND
VPA VNA C4 100nF VCC C6 .27uF VCC RING_DET TIP R3 ISO1 2 PRI 1 671-8005 RING R5 22K SIDAC RV1 RING 3 T1 C7 .033UF SEC 4 5.1K TIP R2 21K 100nF C5 2 CATHODE C/A ANODE 3 1
To --> RS232 level shifter --> Host microprocessor VPA VNA VREF VBG HBDEN 20 17 16 15 21 18 19 14 RXA TXAP TXAN
10 9 8 7 6 5 4 3 2 1 7 8 9 4 10 32 31 30 27 1 28
USR11 USR10/LIU
RI NG RELAY
HEADER 10
GND
DCD DSR CTS RI RTS DTR RXC RXD TXD ASRCH TXC D1 DUAL_DIODES
U2 1 2 3 4 5 6 RJ1 RJ2 RJ3 RJ4 RJ5 RJ6 RJ11
11 12 2 3
R4
470
6
5
4
TYPICAL USA APPLICATION SCHEMATICS
1
1
2
+ GND R6 1K
C9
3
GND
DECOUPLING FOR U3 2901
2
12
VCC C8 0.1UF R7 470
VCC
U3 HOOK_SW
C10 0.1UF
10uF
VCC
R9
0
R8 10K
VPA
R10
0
C11 0.1UF
C12
+
10uF
GND
VNA
GND
This document contains information proprietary to TDK Semiconductor Corp. Any disclosure or use is expressly prohibited, except upon explicit written permission by TDK Semiconductor Corp.
Title TDK 73M2901 + US line interface Size B Date: Document Number Monday, July 31, 2000 Sheet 1 of 2 Rev 1.0
73M2901/3.3V Advanced Single Chip Modem
BER VS SNR
BER VS RECEIVE LEVEL
V.22bis 3002A Line, 3.3V, 25C
1.00E+00
V.22bis 3002A Line, 3.3V, 25C
1.00E+00
1.00E-01
Answer
1.00E-01
Origina te Answer Origina te
1.00E-02 Bit Error Rate
Bit Error Rate
1.00E-02
1.00E-03
1.00E-03
1.00E-04
1.00E-04
1.00E-05
1.00E-05
1.00E-06
10 11 12 13 14 15 16 17 18 19
1.00E-06
4 8 12 16 20 24 28 32 36 40 44
SNR (Rx Signal/ 3k Hz) (dB)
Receive Level (dBm)
13
73M2901/3.3V Advanced Single Chip Modem
32 PIN PLCC PIN-OUT PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN NAME
ASRCH RING RELAY RI
PIN 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PIN NAME TXAP VREF VBG RXA VNA VND OSCOUT OSCIN VPD VND TXD TXCLK VPD RXD RXCLK
DTR
VND VPD
DCD DSR CTS RTS
USR11 USR10 RESET HBDEN VPA TXAN
44 PIN TQFP PIN-OUT PIN 1 2 3 4 5 6 7 8 9 10 11 PIN NAME N/C VPD
DCD DSR CTS RTS
PIN 12 13 14 15 16 17 18 19 20 21 22
PIN NAME VPD N/C N/C HBDEN VPA TXAN TXAP VREF VBG RXA VNA
PIN 23 24 25 26 27 28 29 30 31 32 33
PIN NAME N/C VND OSCOUT OSCIN VPD VND N/C TXD TXCLK N/C VPD
PIN 34 35 36 37 38 39 40 41 42 43 44
PIN NAME N/C RXD RXCLK
DTR ASRCH RING RELAY
USR11 USR10 RESET N/C VND
N/C N/C
RI
VND
14
73M2901/3.3V Advanced Single Chip Modem
MECHANICAL DRAWINGS
0.453 (11.51) 0.449 (11.40)
PIN NO. 1 IDENT.
0.595 (15.11) 0.585 (14.86)
0.553 (14.05) 0.549 (13.94)
0.495 (12.57) 0.485 (12.32) 0.023 0.029
0.140 (3.56) 0.123 (3.12) 0.050 0.013 0.021 0.300 REF (7.62 REF) 0.430 (10.92) 0.390 (9.91) 0.045 (1.140) 0.020 (0.508)
0.095 (2.41) 0.078 (1.98)
0.026 0.032 0.400 REF (10.16 REF)
0.530 (13.46) 0.490 (12.45)
32-Pin PLCC
15
73M2901/3.3V Advanced Single Chip Modem
MECHANICAL DRAWINGS (continued)
12.0 BSC (0.48)
12.0 BSC (0.48)
INDEX 1
10.0 BSC (0.40)
1.60 (0.064)
0.09 (0.035) 0.20 (0.008)
0.37 (0.0148) Typ. 0.80 (0.032) Typ.
0.60 (0.024) Typ.
44-Pin TQFP (JEDEC LQFP)
16
73M2901/3.3V Advanced Single Chip Modem
PACKAGE PIN DESIGNATIONS (Top View)
CAUTION: Use handling procedures necessary for a static sensitive component.
32-Lead PLCC 73M2901-32IH/3
44-Pin TQFP 73M2901-IGT/3
ORDERING INFORMATION
PART DESCRIPTION 73M2901/3.3V 32-Pin Plastic Leaded Chip Carrier 73M2901/3.3V 44-Pin Thin Quad Flat Pack ORDER NUMBER 73M2901-32IH/3 73M2901-IGT/3 PACKAGING MARK 73M2901-32IH 73M2901-IGT
No responsibility is assumed by TDK Semiconductor Corporation for use of this product nor for any infringements of patents and trademarks or other rights of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of TDK Semiconductor Corporation, and the company reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet is current before placing orders. TDK Semiconductor Corp., 2642 Michelle Dr., Tustin, CA 92780, (714) 508-8800, FAX (714) 508-8877, www.tdksemiconductor.com TDK Semiconductor Corporation 12/12/00 Rev. B
17

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